A liquid crystal display panel includes an array of a plurality of pixels, and a plurality of gate lines and a plurality of data lines for driving image display of the pixels. The liquid crystal display panel further includes a gate driving circuit for outputting gate scanning signals to the plurality of gate lines. The gate driving circuit converts an input clock signal through a shift register into an on/off voltage, and sequentially applies it to the gate line.
FIGS. 1A-1B are diagrams illustrating the structure of conventional shift register units. Referring to FIG. 1A, in a reset phase and an output stop holding phase, the pull down node PD is provided with a clock signal CLKB′. The pull down node PD is connected to the gate electrodes of thin film transistors T5 and T6 for noise reduction. Referring to FIG. 1B, in a reset phase and an output stop holding phase, the pull down node PD is provided with a high voltage level signal VDD. The pull down node PD is connected to the gate electrodes of thin film transistors T5 and T6 for noise reduction. In FIGS. 1A-1B, “INPUT” denotes an input terminal, “RESET” denotes a reset terminal. “PU” denotes a pull up node, “PD_CN” denotes a pull down control node, “OUT” denotes an output terminal for gate scanning signal, “VSS” denotes a low voltage signal, “CLK” denotes a clock signal, T1 is an input thin film transistor, T2 is a first reset thin film transistor, T3 is a pull up thin film transistor, T4 is a second reset thin film transistor, T7 is a first pull down node control thin film transistor, T8 is a second pull down node control thin film transistor, T9 is a first pull down control node control thin film transistor, and T10 is a second pull down control node control thin film transistor.